32186 datasheet(961/1032 Pages) RENESAS

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ELECTRICAL CHARACTERISTICS

23-45

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Symbol

Parameter

Rated Value

Unit See Fig.

MIN

MAX

23.10.5

tc(CLK)

CLK Input Cycle Time

× tc(BCLK)

[7]

Timing

tw(CLKH) CLK Input "H" Pulse Width

× tc(BCLK)

[8]

requirements

tw(CLKL) CLK Input "L" Pulse Width

× tc(BCLK)

[9]

tsu(D-CLK) RXD Input Setup Time

[10]

th(CLK-D) RXD Input Hold Time

55+tc(BCLK)

[11]

Switching

td(CLK-D) TXD Output Delay Time

When 3 point sampling is invalid

85+2tc(BCLK)

[12]

characteristics

When 3 point sampling is valid

85+3tc(BCLK)

23.10 A.C. Characteristics (when VCCE = 3.3 V)

SCLKO

TXD

RXD

[6] td(CLK-D)

[4] tsu(D-CLK)

[5] th(CLK-D)

a) CSIO mode, with internal clock selected

0.8VCCE

0.2VCCE

0.8VCCE

0.2VCCE

0.8VCCE

b) CSIO mode, with external clock selected

SCLKI

TXD

RXD

[12] td(CLK-D)

[10] tsu(D-CLK)

[11] th(CLK-D)

0.8VCCE

0.2VCCE

0.8VCCE

0.2VCCE

0.8VCCE

0.2VCCE

0.8VCCE

[7] tc(CLK)

[8] tw(CLKH)

[9] tw(CLKL)

0.2VCCE

0.8VCCE

[98] th(CLK-D)

Figure 23.10.5 Serial Interface Timing

(5) Serial interface

a) CSIO mode, with internal clock selected

b) CSIO mode, with external clock selected

Symbol

Parameter

Rated Value

Unit See Fig.

MIN

MAX

23.10.5

Timing

tsu(D-CLK) RXD Input Setup Time

When 3 point sampling is invalid

[4]

When 3 point sampling is valid

80+tc(BCLK)

requirements

th(CLK-D) RXD Input Hold Time

15+tc(BCLK)

[5]

Switching

td(CLK-D) TXD Output Delay Time

[6]

characteristics th(CLK-D) TXD Hold Time

[98]

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