32186 datasheet(1007/1032 Pages) RENESAS

1007 / 1032 page

SUMMARY OF PRECAUTIONS

Appendix 4

Appendix 4-17

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Appendix 4.9 Notes on Multijunction Timers

Appendix 4.9.16 0% or 100% Duty-Cycle Wave Output during PWM Output and Single-

shot PWM Output Modes

During PWM output or single-shot PWM output mode, if the value "H'FFFF" is written to the reload 0 or reload 1

Because determination is made to see if the reload value is "H'FFFF" during PWM output or single-shot PWM

output mode, following precautions must be observed.

(1) Because the counter counts one even when detecting 0% or 100% duty-cycle, one of the two reload

registers must have set in it one less than the intended value in order for a constant-cycle waveform to be

produced.

Example: If the desired output cycle is 10 counts

Cycle ratio

50% : 50%

80% : 20%

90% : 10%

100% : 0%

Count ratio

5 : 5

8 : 2

9 : 1

10 : 0

0004 : 0004

0007 : 0001

0008 : 0000

0009 : FFFF

Because the counter counts n + 1, the values actually set in the

respective registers must be one less than the intended value.

(2) Because setting the value "H'FFFF" in the reload register produces a 0% or 100% duty-cycle, it is impos-

sible to count the exact "H'FFFF."

(3) Setting the value "H'FFFF" in both reload 0 and reload 1 registers is inhibited.

(4) Writing the value "H'FFFF" to the counter while in operation is inhibited.

(5) Even for a 0% or 100% duty-cycle, interrupt requests and startup registers to other timers are generated.

(6) Because a 0% or 100% duty-cycle needs to be determined when reloading the counter, there is a one count

clock equivalent delay before F/F is inverted and an interrupt or DMA transfer request is generated. How-

ever, startup requests to other timers are not delayed.

0008: FFFF

The counter counts one without inverting

F/F output after detecting "FFFF." For

this reason, the value to be set in the

Appendix 4.9.15 Notes on using TOU continuous output mode

The following describes precautions to be observed when using TOU continuous output mode.

• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable

bit, the latter has priority so that count is disabled.

• If the counter is accessed for read at the cycle of underflow, the counter value is read out as H'FF FFFF but

changes to “reload register value -1” at the next count clock timing.

• Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is

generated before F/F output is inverted after writing the enable bit.

32186 Datasheet(PDF) 1007 Page - Renesas Technology Corp

32186 Datasheet(HTML) 1007 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL