32186 datasheet(1014/1032 Pages) RENESAS

1014 / 1032 page

SUMMARY OF PRECAUTIONS

Appendix 4

Appendix 4-24

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Appendix 4.10 Notes on A/D Converter

Appendix Table 4.10.1 Sampling Time (in Which C2 Needs to Be Charged)

Conversion start method

Conversion speed

Sampling time

Sampling time for the

for the first bit

2nd and subsequent bits

2BCLK mode Single mode

Slow mode

Normal speed

55BCLK

27BCLK

(when sample-and-hold

Double speed

31BCLK

15BCLK

disabled or normal

Fast mode

Normal speed

23BCLK

11BCLK

sample-and-hod enabled

Double speed

15BCLK

7BCLK

Single mode

Slow mode

Normal speed

55BCLK

–

(when fast sample-

Double speed

31BCLK

–

and-hold enabled)

Fast mode

Normal speed

23BCLK

–

Double speed

15BCLK

–

Comparator mode

Slow mode

Normal speed

55BCLK

–

Double speed

31BCLK

–

Fast mode

Normal speed

23BCLK

–

Double speed

15BCLK

–

Simultaneous

Slow mode

Normal speed

55BCLK

–

sampling

Double speed

31BCLK

–

Fast mode

Normal speed

23BCLK

–

Double speed

15BCLK

–

Therefore, the time in which C2 needs to be charged is found from Eq. B-1, as follows:

Sampling time (in which C2 needs to be charged) > Cin

× R1 + C2(R1 + R2) ----Eq. B-2

Thus, the maximum value of R1 can be obtained as a criterion from the equation below. Note, however, that for

single mode (when sample-and-hold is disabled), the sampling time for the second and subsequent bits (C2

charging time) must be applied.

C2 charging time - C2

× R2

R1 <

Cin + C2

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