32186 datasheet(120/1032 Pages) RENESAS

120 / 1032 page

EIT

4-18

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

4.10 Trap Processing

Figure 4.10.1 Example of a Return Address for Trap (TRAP)

H'00

Address

H'04

H'08

H'0C

H'00

Address

H'04

H'08

H'0C

BPC

H'0A

BPC

H'08

TRAP instruction

Return

address

Return

address

TRAP instruction

4.10 Trap Processing

4.10.1 Trap

[Occurrence Conditions]

Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen traps

are generated, each corresponding to one of TRAP instruction operands 0–15. Accordingly, sixteen

vector entries are provided.

[EIT Processing]

(1) Saving SM, IE and C bits

The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC.

BSM

←

BIE

←

(2) Updating SM, IE and C bits

The PSW register’s SM, IE and C bits are updated as shown below.

←

Unchanged

←

(3) Saving the PC

When the trap instruction is executed, the PC value of TRAP instruction + 4 is set in the BPC register.

For example, if the TRAP instruction is located at address 4, the value H’08 is set in the BPC register.

Similarly, if the TRAP instruction is located at address 6, the value H’0A is set in the BPC register.

The value of the BPC register bit 30 indicates whether the trap instruction resides on a word boundary

(BPC register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1").

However, in either case of the above, the address to which the RTE instruction returns after the EIT

handler has terminated is address 8. (This is because the 2 low-order address bits are cleared to "00"

when returned to the PC.)

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