32186 datasheet(117/1032 Pages) RENESAS

117 / 1032 page

EIT

4-15

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

4.9 Interrupt Processing

4.9.1 Reset Interrupt (RI)

[Occurrence Conditions]

A reset interrupt is accepted in machine cycle by pulling the RESET# input signal "L." The reset

interrupt is assigned the highest priority among all EITs.

[EIT Processing]

(1) Initializing SM, IE and C bits

The PSW register’s SM, IE and C bits are initialized as shown below.

←

For the reset interrupt, the values of BSM, BIE and BC bits are undefined.

(2) Branching to the EIT vector entry

The CPU branches to the address H’0000 0000 in the user space. However, when operating in boot

mode, the CPU jumps to the boot program. For details, see Section 6.6, “Programming the Internal

Flash Memory.”

(3) Jumping from the EIT vector entry to the user program

The CPU executes the instruction written by the user at the address H’0000 0000 of the EIT vector

entry. In the reset vector entry, be sure to initialize the PSW and SPI registers before jumping to the

start address of the user program.

4.9.2 System Break Interrupt (SBI)

System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a

fault condition is notified by an external watchdog timer. The system break interrupt cannot be masked by

the PSW register IE bit.

Therefore, the system break interrupt can only be used when the system has some fatal event already

existing in it when the interrupt is detected. Also, this interrupt must be used on condition that after pro-

cessing by the SBI handler, control will not return to the program that was being executed when the system

break interrupt occurred.

[Occurrence Conditions]

A system break interrupt is accepted by a falling edge on SBI# input pin. (The system break interrupt

cannot be masked by the PSW register IE bit.)

In no case will a system break interrupt be activated immediately after executing a 16-bit instruction

that starts from a word boundary. (For 16-bit branch instructions, however, the interrupt is accepted

immediately after branching.) Note also that because of the instruction processing-completed type, a

system break interrupt is accepted after the instruction is completed.

32186 Datasheet(PDF) 117 Page - Renesas Technology Corp