32186 datasheet(118/1032 Pages) RENESAS

118 / 1032 page

EIT

4-16

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

4.9 Interrupt Processing

16-bit instruction

Order in which instructions are executed

32-bit instruction

Address 1000

Address 1002

Address 1004

Address 1008

Interrupt may

be accepted

Interrupt cannot

be accepted

16-bit instruction

Interrupt may

be accepted

Interrupt may

be accepted

Figure 4.9.1 Timing at Which System Break Interrupt (SBI) is Accepted

[EIT Processing]

(1) Saving SM, IE and C bits

The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC.

BSM

←

BIE

←

(2) Updating SM, IE and C bits

The PSW register’s SM, IE and C bits are updated as shown below.

←

(3) Saving the PC

The address of the next instruction (always on word boundary) following one in which the interrupt

was detected is stored in the BPC register. If the interrupt was detected in a branch instruction, then

the next instruction is one that exists at the jump address.

(4) Branching to the EIT vector entry

The CPU branches to the address H’0000 0010 in the user space. This is the last operation performed

in hardware preprocessing.

(5) Jumping from the EIT vector entry to the user-created handler

The CPU executes the BRA instruction written by the user at the address H’0000 0010 of the EIT

vector entry to jump to the start address of the user-created handler.

The system break interrupt can only be used when the system has some fatal event already existing

in it when the interrupt is detected. Also, this interrupt must be used on condition that after processing

by the SBI handler, control will not return to the program that was being executed when the system

break interrupt occurred.

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