32186 datasheet(129/1032 Pages) RENESAS

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INTERRUPT CONTROLLER (ICU)

5-5

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

5.2 ICU Related Registers

5.2.1 Interrupt Vector Register

Interrupt Vector Register (IVECT)

<Address: H’0080 0000>

123456789

b15

IVECT

????????????????

Bit Name

Function

−15

IVECT

When an interrupt request is accepted, the 16-low-order

16 low-order bits of ICU vector table address

bits of the ICU vector table address for the accepted

interrupt request source are stored in this register.

Note: • This register must always be accessed in halfwords (2 bytes). (This is a read-only register.)

The Interrupt Vector Register (IVECT) is used when an interrupt request is accepted to store the 16-low-

order bits of the ICU vector table address for the accepted interrupt request source.

Before this function can work, the ICU vector table (addresses H’0000 0094 through H’0000 013B) must

have set in it the start addresses of interrupt handlers for each internal peripheral I/O. When an interrupt

request is accepted, the 16-low-order bits of the ICU vector table address for the accepted interrupt re-

quest source are stored in the IVECT register. In the EIT handler, read the content of this IVECT register

using the LDH instruction to get the ICU vector table address.

When the IVECT register is read, operations (1) to (4) below are automatically performed in hardware.

(1) The interrupt priority level of the accepted interrupt request source (ILEVEL) is set in the IMASK regis

ter as a new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt

request source are masked.)

(2) The interrupt request bit for the accepted interrupt request source is cleared (not cleared for level-

recognized interrupt request sources).

(3) The interrupt request (EI) to the CPU core is dropped.

(4) The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution).

Notes: • Do not read the Interrupt Vector Register (IVECT) in the EIT handler unless interrupts are dis

abled (PSW register IE bit = "0"). In the EIT handler, furthermore, read the Interrupt Request

Mask Register (IMASK) first before reading the IVECT register.

• To reenable interrupts (by setting the IE bit to "1") after reading the Interrupt Vector Register

(IVECT), execute the following processing in the order given:

(1) Read the Interrupt Vector Register (IVECT)

(2) Perform a read access to the SFR at least once

(3) Perform a dumy access to the internal memory, SFR, etc. at least once

(4) Enable interrupts (by setting the IE bit to "1")

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