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32186 Datasheet(PDF) 133 Page - Renesas Technology Corp |
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32186 Datasheet(HTML) 133 Page - Renesas Technology Corp |
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133 / 1032 page ![]() INTERRUPT CONTROLLER (ICU) 5 5-9 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 5.2 ICU Related Registers 9 1011121314 b15) (b8 123456 b7 b0 ILEVEL IREQ 0 111 0 0 0 0 <Upon exiting reset: H’07> b Bit Name Function R W 0–2 No function assigned. Fix to "0" 00 (8–10) 3 IREQ <When edge-recognized> R W (11) Interrupt request bit At read 0: Interrupt not requested 1: Interrupt requested At write 0: Clear interrupt request 1: Generate interrupt request <When level-recognized> R 0 At read 0: Interrupt not requested 1: Interrupt requested 4 No function assigned. Fix to "0" 00 (12) 5–7 ILEVEL 000: Interrupt priority level 0 R W (13–15) Interrupt priority level bits 001: Interrupt priority level 1 010: Interrupt priority level 2 011: Interrupt priority level 3 100: Interrupt priority level 4 101: Interrupt priority level 5 110: Interrupt priority level 6 111: Interrupt priority level 7 (interrupt disabled) (1) IREQ (Interrupt Request) bit (Bit 3 or 11) When an interrupt request from some internal peripheral I/O occurs, the corresponding IREQ (Inter- rupt Request) bit is set to "1." This bit can be set and cleared in software for only edge-recognized interrupt request sources (and not for level-recognized interrupt request sources). Also, when this bit is set by an edge-recognized interrupt request generated, it is automatically cleared to "0" by reading the Interrupt Vector Register (IVECT) (not cleared in the case of level-recognized interrupt request). If the IREQ bit is cleared in software at the same time it is set by an interrupt request generated, clearing in software has priority. Also, if the IREQ bit is cleared by reading the Interrupt Vector Regis- ter (IVECT) at the same time it is set by an interrupt request generated, clearing by a read of the IVECT register has priority. Note: • External Interrupt (EI) to the CPU core is not deasserted by clearing the IREQ bit. External Interrupt (EI) to the CPU core can only be deasserted by the following operation: (1) Reset (2) IVECT register read (3) Write to the IMASK register |
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