 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
32186 Datasheet(PDF) 135 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
32186 Datasheet(HTML) 135 Page - Renesas Technology Corp |
|
|
135 / 1032 page  INTERRUPT CONTROLLER (ICU) 5 5-11 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 5.3 Interrupt Request Sources in Internal Peripheral I/O The Interrupt Controller receives as inputs the interrupt requests from MJT (multijunction timer), DMAC, serial interface, A/D converter, RTD, CAN, DRI and RAM write monitor. For details about these interrupts, see each section in which the relevant internal peripheral I/O is described. Table 5.3.1 Interrupt Request Sources in Internal Peripheral I/O Interrupt Request Sources Contents Number of ICU Type of Input Input Sources Source ( Note 1) MJT input interrupt 4 MJT input interrupt group 4 (TIN3–TIN6 inputs) 4 Level-recognized MJT input interrupt 3 MJT input interrupt group 3 (TIN20–TIN27 inputs) 8 Level-recognized MJT input interrupt 2 MJT input interrupt group 2 (TIN16–TIN19 inputs) 4 Level-recognized MJT input interrupt 1 MJT input interrupt group 1 (TIN0 input) 1 Level-recognized MJT input interrupt 0 MJT input interrupt group 0 (TIN7–TIN11 inputs) 5 Level-recognized MJT output interrupt 7 MJT output interrupt group 7 (TMS0, TMS1 output) 2 Level-recognized MJT output interrupt 6 MJT output interrupt group 6 (TOP8, TOP9 output) 2 Level-recognized MJT output interrupt 5 MJT output interrupt group 5 (TOP10 output) 1 Edge-recognized MJT output interrupt 4 MJT output interrupt group 4 (TIO4–TIO7 outputs) 4 Level-recognized MJT output interrupt 3 MJT output interrupt group 3 (TIO8, TIO9 outputs) 2 Level-recognized MJT output interrupt 2 MJT output interrupt group 2 (TOP0–TOP5 outputs) 6 Level-recognized MJT output interrupt 1 MJT output interrupt group 1 (TOP6, TOP7 outputs) 2 Level-recognized MJT output interrupt 0 MJT output interrupt group 0 (TIO0–TIO3 outputs) 4 Level-recognized DMA0–4 interrupt DMA0–4 transfer-completed 5 Level-recognized SIO1 receive interrupt SIO1 reception-completed or receive error interrupt 1 Edge-recognized SIO1 transmit interrupt SIO1 transmission-completed or transmit buffer empty interrupt 1 Edge-recognized SIO0 receive interrupt SIO0 reception-completed or receive error interrupt 1 Edge-recognized SIO0 transmit interrupt SIO0 transmission-completed or transmit buffer empty interrupt 1 Edge-recognized A/D0 conversion interrupt A/D0 conversion (single mode, scan single-shot mode, or 1 cycle 1 Edge-recognized of scan continuous mode) completed and comparate-completed TID0 output interrupt TID0 output 1 Edge-recognized TOU0 output interrupt TOU0_0–TOU0_7 outputs 8 Level-recognized DMA5–9 interrupt DMA5–9 transfer-completed 5 Level-recognized SIO2,3 transmit/receive interrupt SIO2,3 reception-completed or receive error interrupt, 4 Level-recognized transmission-completed or transmit buffer empty interrupt RTD interrupt RTD interrupt generation command 1 Edge-recognized TID1 output interrupt TID1 output 1 Edge-recognized TOU1 output interrupt TOU1_0–TOU1_7 outputs 8 Level-recognized SIO4,5 transmit/receive interrupt SIO4,5 reception-completed or receive error interrupt, 4 Level-recognized transmission-completed or transmit buffer empty interrupt TML1 input interrupt TML1 input (TIN30–TIN33 inputs) 4 Level-recognized CAN0 transmit/receive & error CAN0 transmission or reception completed, CAN0 bus error, 67 Level-recognized interrupt CAN0 error passive, CAN0 bus-off, CAN0 single-shot CAN1 transmit/receive & error CAN1 transmission or reception completed, CAN1 bus error, 67 Level-recognized interrupt CAN1 error passive, CAN1 bus-off, CAN1 single-shot DRI transfer interrupt DRI address counter 0 transfer-completed, 5 Level-recognized DRI address counter 1 transfer-completed, overrun error, latch enable error and DRI transfer counter underflow DRI counter interrupt DEC0–DEC4 underflow 5 Level-recognized DRI event detection interrupt DIN0–DIN5 event detected 6 Level-recognized CAN0 transmit/receive interrupt CAN0 transmission-completed, CAN0 reception-completed 32 Level-recognized CAN0 single-shot interrupt CAN0 single-shot 32 Level-recognized CAN0 error interrupt CAN0 bus error, CAN0 error passive, CAN0 bus off 3 Level-recognized CAN1 transmit/receive interrupt CAN1 transmission-completed, CAN1 reception-completed 32 Level-recognized CAN1 single-shot interrupt CAN1 single-shot 32 Level-recognized CAN1 error interrupt CAN1 bus error, CAN1 error passive, CAN1 bus off 3 Level-recognized RAM write monitor interrupt RAM write 16 Level-recognized Note 1: ICU type of input source • Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal supplied to the ICU. • Level-recognized: Interrupt requests are generated when the interrupt signal supplied to the ICU is held "L." For this type of interrupt, the ICU’s Interrupt Control Register IRQ bit cannot be set or cleared in software. 5.3 Interrupt Request Sources in Internal Peripheral I/O |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
