32186 datasheet(137/1032 Pages) RENESAS

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INTERRUPT CONTROLLER (ICU)

5-13

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Figure 5.5.1 Example of Priority Resolution when Accepting Interrupt Requests

Table 5.5.1 ILEVEL Settings and Accepted IMASK Values

ILEVEL values set

IMASK values at which interrupts are accepted

0 (ILEVEL = "000")

Accepted when IMASK is 1–7

1 (ILEVEL = "001")

Accepted when IMASK is 2–7

2 (ILEVEL = "010")

Accepted when IMASK is 3–7

3 (ILEVEL = "011")

Accepted when IMASK is 4–7

4 (ILEVEL = "100")

Accepted when IMASK is 5–7

5 (ILEVEL = "101")

Accepted when IMASK is 6–7

6 (ILEVEL = "110")

Accepted when IMASK is 7

7 (ILEVEL = "111")

Not accepted (interrupts disabled)

5.5 Description of Interrupt Operation

5.5.1 Acceptance of Internal Peripheral I/O Interrupts

An interrupt request from any internal peripheral I/O is checked to see whether or not to accept by compar-

ing its ILEVEL value set in the Interrupt Control Register and the IMASK value of the Interrupt Request

Mask Register. If its priority is higher than the IMASK value, the interrupt request is accepted. However, if

two or more interrupt requests occur simultaneously, the Interrupt Controller resolves priority between

these interrupt requests following the procedure described below.

1) The ILEVEL values set in the Interrupt Control Registers for the respective internal peripheral I/Os are

compared with each other.

2) If the ILEVEL values are the same, priorities are resolved according to the predetermined hardware priority.

3) The ILEVEL and IMASK values are compared.

If two or more interrupt requests occur simultaneously, the Interrupt Controller first compares their priority levels

set in each Interrupt Control Register’s ILEVEL bit to select an interrupt request that has the highest priority. If

the interrupt requests have the same ILEVEL value, their priorities are resolved according to the hardware fixed

priority. The interrupt request thus selected has its ILEVEL value compared with the IMASK value and if its

priority is higher than the IMASK value, the Interrupt Controller sends an EI request to the CPU.

Interrupt requests may be masked by setting the Interrupt Request Mask Register and the Interrupt Control

5.5 Description of Interrupt Operation

Interrupt

requested

or not

Resolve priority

according to

Interrupt Priority

Level (ILEVEL)

Resolve priority

according to

hardware priority

Compare with

IMASK value

TIN3 input interrupt request

(MJT input interrupt 4)

TIO5 output interrupt request

(MJT output interrupt 4)

TOP8 output interrupt request

(MJT output interrupt 6)

SIO0 transmit interrupt request

DMA1 interrupt request

(DMA0-4 interrupt)

A/D0 conversion interrupt request

(ILEVEL settings)

Level 3

Level 4

Level 5

Level 3

Level 1

Level 3

Not requested

Requested

Hardware

fixed priority

Accept interrupt

if PSW register

IE bit = 1

Level 3

Can be accepted

when IMASK = 4-7

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