32186 datasheet(140/1032 Pages) RENESAS

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INTERRUPT CONTROLLER (ICU)

5-16

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Figure 5.5.2 Typical Handler Operation for Interrupts from Internal Peripheral I/O

5.5 Description of Interrupt Operation

Note 1: For operations at EIT acceptance and return from EIT, also see Section 4.3, "EIT Processing Procedure."

Note 2: Do not read the Interrupt Vector Register (IVECT) or write to the Interrupt Request Mask Register (IMASK)

in the EIT handler unless interrupts are disabled (PSW register IE bit = 0).

Note 3: To enable multiple interrupts, execute processing in [6] and [9].

Note 4: There are precautions to be taken when reenabling interrupts (by setting the IE bit to "1") after reading the

Interrupt Vector Register (IVECT). For details, see the Section 5.2.1, "Interrupt Vector Register (IVECT)."

The precautions apply to the Process [4], therefore, other processes are not required to add.

Also, there are precautions to be taken when reenabling interrupts (by setting the IE bit to "1") after writing

to the Interrupt Request Mask Register (IMASK). For details, see the Section 5.2.2, "Interrupt Request Mask

H'0000 0080

BRA instruction

Read Interrupt Vector

Read ICU vector table

Branch to the interrupt handler

for each internal peripheral I/O

RTE

H'0080 0004

H'0000 0094

H'0000 013B

Interrupt

handler

EI (External Interrupt)

handler

EI (External Interrupt)

vector entry

Interrupt handler

start address

Program being

executed

Interrupt

generated

IVECT

Save BPC to the stack

Save PSW to the stack

Save general-purpose

registers to the stack

Restore BPC from the stack

Restore PSW from the stack

Restore general-purpose

registers from the stack

Read and save Interrupt

Request Mask Register

(IMASK) to the stack

IMASK

H'0080 0000

Set PSW register IE bit to 1

Clear PSW register

IE bit to 0

Restore Interrupt Request

Mask Register (IMASK)

from the stack

[1]

[2]

[3]

[5]

[7]

[8]

[9]

[6]

[10]

[11]

ICU vector table

(Note 1)

Hardware preprocessing

when EIT is accepted

Hardware postprocessing

when RTE instruction

is executed

Read and overwrite

Interrupt Request Mask

[4]

[12]

(Note 2)

(Note 3)

(Note 4)

(Note 3)

(Note 2)

Interrupt

handler

[1] to [12]: Processing of EI

by interrupt handler

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