32186 datasheet(197/1032 Pages) RENESAS

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INTERNAL MEMORY

6-55

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

6.11 Notes on Internal RAM

Precautions about the Internal Memory is shown below.

• The writes from DRI,RTD to internal RAM uncompete with access from other bus masters (CPU, DMA, NBD,

SDI), because of using dedicated bus not M32R-FPU.

But in case DRI,RTD transfers and access from other bus masters for area in 16-Kbyte of internal RAM

occur at same time, access competition occurs.

When access competition occurs, arbitration is performed according to the following priority.

NBD/SDI > DMA > CPU > DRI > RTD

• When started by boot mode, internal RAM value is indefinite after started by boot mode in order to "Flash

writing/ Erase program" is transferd to internal RAM.

6.12 Notes on Internal Flash Memory

The following describes precautions to be taken when programming/erasing the internal flash memory.

• When the internal flash memory is programmed or erased, a high voltage is generated internally. Because

mode transitions during programming/erase operation may cause the chip to break down, make sure the mode

setting/reset pin and power supply voltages do not fluctuate to prevent unintended changes of modes.

• If the system uses any pins that are to be used by a general-purpose programming/erase tool, care must be

taken to prevent adverse effects on the system when the tool is connected.

• If the internal flash memory needs to be protected while using a general-purpose programming/erase tool, set

any ID in the flash memory protect ID verification area (H’0000 0084 to H’0000 008F).

• If the internal flash memory does not need to be protected while using a general-purpose programming/erase

tool, fill the entire flash memory protect ID verification area (H’0000 0084 to H’0000 008F) with H’FF.

• If the Flash Status Register (FSTAT)’s each error status is to be cleared (initialized to H’80) by resetting the

Flash Control Register 4 (FCNT4) FRESET bit, check to see that the Flash Status Register (FSTAT) FBUSY bit

= "1" (ready) before clearing the error status.

• Before resetting the Flash Control Register 1 (FCNT1) FENTRY bit from "1" to "0," check to see that the Flash

Status Register (FSTAT) FBUSY bit = "1" (ready).

• Do not clear the FENTRY bit if the Flash Control Register 1 (FCNT1) FENTRY bit = "1" and the Flash Status

• When programming/erasing via JTAG, the flash memory can be programmed or erased regardless of the pin

state because the FP pin is controlled internally within the chip.

32186 Datasheet(PDF) 197 Page - Renesas Technology Corp