32186 datasheet(243/1032 Pages) RENESAS

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INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-41

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

8.7 Port Peripheral Circuits

P84(SCLKI0/SCLKO0/TO24)

P87(SCLKI1/SCLKO1/TO21)

P93(TO16/SCLKI5/SCLKO5)

P105(TO13/SCLKI4/SCLKO4/DD2)

Port input data selection

Data bus

Peripheral function output

Direction register

Port output latch

Operation mode register

Input function

enable

Data bus

SCLKIi input (Note 2)

SCLKOi output

Direction register

Port output latch

Operation mode register

Port

input level

switching

function

(Standard:

peripheral

schmitt)

Input function

enable

(Note 1)

UART/CSIO

function select bit

Internal/external

clock select bit

Peripheral function

select register

Peripheral function output

Port input level

switching function

(Standard:

no peripheral input)

(Note 1)

Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function."

Note 2: "H" level is entered to the peripheral function input when it is set to the general-purpose port in the operation

mode register.

Notes: • The circle denotes a pin.

• The symbol

denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed

the VCCE or VCC-BUS voltage.

• The input capacitance of each pin is approximately 10 pF.

• The logic of peripheral function select register for P93, P105 are reversal, but it is not mentioned

in this clock diagram.

• DRI relative pin is not mentioned in this clock diagram.

P00-P07(DB0/TO21/DD0

-DB7/TO28/DD7)

P10-P17(DB8/TO29/DD8

-DB15/TO36/DD15)

P96(TO19/DD13)

P97(TO20/DD12)

P100(TO8)

Figure 8.7.3 Port Peripheral Circuit Diagram (3)

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