32186 datasheet(241/1032 Pages) RENESAS

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INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-39

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

8.7 Port Peripheral Circuits

Figures 8.7.1 through 8.7.5 show the peripheral circuit diagrams of the input/output ports described in the pre-

ceding pages.

Figure 8.7.1 Port Peripheral Circuit Diagram (1)

Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function."

Note 2: The standard input level of TIN4-TIN11,TIN30-TIN33 is peripheral TTL.

Note 3: "H" level is entered to the peripheral function input when it is set to the general-purpose port in the operation

mode register.

Notes: • During external extension and processor modes, P20-P27, P41-P43, P224 and P225 are

external bus interface control signal pins, but their functional description in this block diagram is omitted.

• The circle denotes a pin.

• The symbol

denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed

the VCCE or VCC-BUS voltage.

• The input capacitance of each pin is approximately 10 pF.

• The logic of peripheral function select register for P83, P86, P124, P125, P126, P127, P134, P137, P150,

P175 are reversal, but it is not mentioned in this clock diagram.

• DRI relative pin is not mentioned in this clock diagram.

P20

−P27(A23/DD24−A30/DD31)

P41(BLW#/BLE#)

P42(BHW#/BHE#)

P43(RD#)

P61

−P63

P225(A12/CS3#)

P224(A11/CS2#)

P30(A15/TIN4/DD16)

P31(A16/TIN5/DD17)

P32(A17/TIN6/DD18)

P33(A18/TIN7/DD19)

P34(A19/TIN30/DD20)

P35(A20/TIN31/DD21)

P36(A21/TIN32/DD22)

P37(A22/TIN33/DD23)

P44(CS0#/TIN8)

P45(CS1#/TIN9)

P46(A13/TIN10)

P47(A14/TIN11)

P73(HACK#/TIN26)

P83(RXD0/TO25)

P86(RXD1/TO22)

P95(TO18/RXD5/DD14)

P101(TO9/CRX0)

P103(TO11/TIN24)

P104(TO12/TIN25/DD3)

P107(TO15/RXD4/DD0)

P124(TCLK0/A9/DD3)

P125(TCLK1/A10/DD2)

P126(TCLK2/CS2#/DD1)

P127(TCLK3/CS3#/DD0)

P134(TIN20/TXD3/DIN4)

P137(TIN23/CTX1)

P150(TIN0/CLKOUT/WR#)

P175(RXD2/TO27)

Port input data selection

Data bus

Port output latch

Input function

enable

Direction register

Data bus

Direction register

Port output latch

Peripheral function

output

Operation mode register

Peripheral function

select register

Peripheral function

input (Note 3)

Port input level

switching function

(Standard:

no peripheral input)

(Note 1)

(Note 1) (Note 2)

Port input data selection

Port input level

switching function

(Standard:

peripheral schmitt)

Input function

enable

8.7 Port Peripheral Circuits

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