32186 datasheet(249/1032 Pages) RENESAS

249 / 1032 page

DMAC

9-3

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Figure 9.1.1 Block Diagram of the DMAC

9.1 Outline of DMAC

DMA0

udf

end

DMA1

udf

end

DMA2

udf

end

DMA3

udf

end

DMA4

udf

end

DMA5

udf

end

DMA6

udf

end

DMA7

udf

end

DMA8

udf

end

DMA9

udf

end

(Note 1) TIN3S

TID1_udf/ovf

TOU1_1irq

(Note 2) DRI(DIN1)

SIO4_RXD

TID0_udf/ovf

(Note 2) CAN0_S0/S31

TOU1_0irq

(Note 2) DRI(DIN0)

(Note 2) SIO4_TXD

(Note 2) A/D0 conversion completed

(Note 1) TIN0S

TIO8_udf

TIN30S

TIO9_udf

(Note 2)

A/D0 conversion

completed

TIO8_udf

Software

start

Software start

(Note 1) TIN18S

Software start

(Note 2) SIO0_TXD

(Note 2) SIO1_RXD

Software start

(Note 2) SIO0_RXD

Software start

DMA0-4

interrupts

DMA5-9

interrupts

(Note 2) SIO2_RXD

Software start

(Note 2) SIO1_TXD

(Note 2) CAN0_S0/S31

Software start

(Note 2) SIO2_TXD

(Note 2) CAN0_S1/S30

Software start

(Note 2) SIO3_RXD

(Note 2) CAN0_S1/S30

(Note 2) DRI(DIN2)

SIO5_TXD

(Note 1) TIN0S

TOU1_6irq

(Note 2) DRI(DIN3)

SIO5_RXD

(Note 1) TIN19S

(Note 2) SIO0_TXD

TOU1_7irq

(Note 1) TIN7S

(Note 2) DRI(DIN4)

(Note 1) TIN20S

TOU0_0irq

(Note 1) TIN8S

(Note 2) DRI(DEC0_udf)

(Note 2) CAN1_S0/S31

TOU0_1irq

(Note 2) SIO1_RXD

(Note 2)

DRI Address counter 0 transfer completed

(Note 2) DRI(DEC1_udf)

TOU0_6irq

(Note 2) CAN1_S0/S31

(Note 2) DRI Latch event counter_udf

(Note 2) DRI(DEC3_udf)

TOU0_7irq

(Note 2) DRI Transfer counter_udf

(Note 2) DRI(DEC4_udf)

(Note 2) DRI(DIN5)

TOU0_2irq

(Note 2) SIO3_TXD

(Note 2)

DRI Address counter 1 transfer completed

(Note 2) DRI(DEC2_udf)

(Note 2) CAN1_S1/S30

Software start

(Note 2) SIO3_TXD

(Note 2) CAN1_S1/S30

0123

Input event bus

Output event bus

3210

0123

Note 1: Indicates edge select input at the timer input pin.

Note 2: Indicates an input signal from each peripheral circuit.

32186 Datasheet(PDF) 249 Page - Renesas Technology Corp

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