32186 datasheet(252/1032 Pages) RENESAS

252 / 1032 page

DMAC

9-6

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

9.2.1 DMA Channel Control Registers

DMA0 Channel Control Register 0 (DM0CNT0)

<Address: H’0080 0410>

123456

SADSL0 DADSL0

MDSEL0

TREQF0

REQSL0

TENL0

TSZSL0

Bit Name

Function

MDSEL0

0: Normal mode

DMA0 transfer mode select bit

1: Ring buffer mode

TREQF0

0: Transfer not requested

R(Note 1)

DMA0 transfer request flag bit

1: Transfer requested

2, 3

REQSL0

00: Software start or one DMA2 transfer completed

DMA0 transfer request source select bit

01: A/D0 conversion completed

10: MJT (TIO8_udf)

11: Extended DMA0 transfer request source select

(DMA0 Channel Control Register 1)

TENL0

0: Disable transfer

DMA0 transfer enable bit

1: Enable transfer

TSZSL0

0: 16 bits

DMA0 transfer size select bit

1: 8 bits

SADSL0

0: Fixed

DMA0 source address direction select bit

1: Increment

DADSL0

0: Fixed

DMA0 destination address direction select bit

1: Increment

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

9.2 DMAC Related Registers

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