32186 datasheet(254/1032 Pages) RENESAS

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DMAC

9-8

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

9.2 DMAC Related Registers

DMA1 Channel Control Register 0 (DM1CNT0)

<Address: H’0080 0420>

123456

SADSL1 DADSL1

MDSEL1

TREQF1

REQSL1

TENL1

TSZSL1

Bit Name

Function

MDSEL1

0: Normal mode

DMA1 transfer mode select bit

1: Ring buffer mode

TREQF1

0: Transfer not requested

R(Note 1)

DMA1 transfer request flag bit

1: Transfer requested

2, 3

REQSL1

00: Software start

DMA1 transfer request source select bit

01: MJT (output event bus 0)

10: Settings inhibited

11: Extended DMA1 transfer request source select

(DMA1 Channel Control Register 1)

TENL1

0: Disable transfer

DMA1 transfer enable bit

1: Enable transfer

TSZSL1

0: 16 bits

DMA1 transfer size select bit

1: 8 bits

SADSL1

0: Fixed

DMA1 source address direction select bit

1: Increment

DADSL1

0: Fixed

DMA1 destination address direction select bit

1: Increment

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

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