32186 datasheet(258/1032 Pages) RENESAS

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DMAC

9-12

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

DMA3 Channel Control Register 0 (DM3CNT0)

<Address: H’0080 0440>

123456

SADSL3 DADSL3

MDSEL3 TREQF3

REQSL3

TENL3

TSZSL3

00000000

Bit Name

Function

MDSEL3

0: Normal mode

DMA3 transfer mode select bit

1: Ring buffer mode

TREQF3

0: Transfer not requested

R(Note 1)

DMA3 transfer request flag bit

1: Transfer requested

2, 3

REQSL3

00: Software start

DMA3 transfer request source select bit

01: SIO0_TXD (transmit buffer empty)

10: SIO1_RXD (reception completed)

11: Extended DMA3 transfer request source select

(DMA3 Channel Control Register 1)

TENL3

0: Disable transfer

DMA3 transfer enable bit

1: Enable transfer

TSZSL3

0: 16 bits

DMA3 transfer size select bit

1: 8 bits

SADSL3

0: Fixed

DMA3 source address direction select bit

1: Increment

DADSL3

0: Fixed

DMA3 destination address direction select bit

1: Increment

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

9.2 DMAC Related Registers

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