32186 datasheet(256/1032 Pages) RENESAS

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DMAC

9-10

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

DMA2 Channel Control Register 0 (DM2CNT0)

<Address: H’0080 0430>

123456

SADSL2 DADSL2

MDSEL2 TREQF2

REQSL2

TENL2

TSZSL2

00000000

Bit Name

Function

MDSEL2

0: Normal mode

DMA2 transfer mode select bit

1: Ring buffer mode

TREQF2

0: Transfer not requested

R(Note 1)

DMA2 transfer request flag bit

1: Transfer requested

2, 3

REQSL2

00: Software start

DMA2 transfer request source select bit

01: MJT (output event bus 1)

10: MJT (TIN18S)

11: Extended DMA2 transfer request source select

(DMA2 Channel Control Register 1)

TENL2

0: Disable transfer

DMA2 transfer enable bit

1: Enable transfer

TSZSL2

0: 16 bits

DMA2 transfer size select bit

1: 8 bits

SADSL2

0: Fixed

DMA2 source address direction select bit

1: Increment

DADSL2

0: Fixed

DMA2 destination address direction select bit

1: Increment

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

9.2 DMAC Related Registers

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