HD64F7047 datasheet(107/764 Pages) RENESAS

107 / 764 page

Rev. 2.00, 09/04, page 67 of 720

5.5

Exceptions Triggered by Instructions

5.5.1

Types of Exceptions Triggered by Instructions

Exception processing can be triggered by trap instruction, illegal slot instructions, and general

illegal instructions, as shown in table 5.9.

Table 5.9

Types of Exceptions Triggered by Instructions

Type

Source Instruction

Comment

Trap instruction

TRAPA



Illegal slot

instructions

Undefined code placed

immediately after a delayed

branch instruction (delay slot) or

instructions that rewrite the PC

Delayed branch instructions: JMP, JSR,

BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF

Instructions that rewrite the PC: JMP, JSR,

BRA, BSR, RTS, RTE, BT, BF, TRAPA,

BF/S, BT/S, BSRF, BRAF

General illegal

instructions

Undefined code anywhere

besides in a delay slot



5.5.2

Trap Instructions

When a TRAPA instruction is executed, trap instruction exception processing starts. The CPU

operates as follows:

1. The status register (SR) is saved to the stack.

2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the

instruction to be executed after the TRAPA instruction.

3. The CPU reads the start address of the exception service routine from the exception processing

vector table that corresponds to the vector number specified in the TRAPA instruction, jumps

to that address and starts excuting the program. This jump is not a delayed branch.

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