HD64F7047 datasheet(129/764 Pages) RENESAS

129 / 764 page

Rev. 2.00, 09/04, page 89 of 720

Program

execution state

Interrupt?

NMI?

User break?

I3 to I0

≤

level 14?

Level 14

interrupt?

Level 1

interrupt?

I3 to I0

≤

level 13?

I3 to I0

level 0?

Yes

IRQOUT = low

Save SR to stack

Save PC to stack

Copy accept-interrupt

level to I3 to I0

IRQOUT = high

Read exception

vector table

Branch to exception

service routine

H-UDI

interrupt?

Yes

Level 15

interrupt?

Notes: I3 to I0 are Interrupt mask bits of status register (SR) in the CPU

IRQOUT is the same signal as interrupt request signal to the CPU (see figure 6.1).

Therefore,

IRQOUT is output when the request priority level is higher than the level in bits I3–I0 of SR.

*2 When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when

the CPU starts interrupt exception processing instead of instruction execution (namely, before saving SR to stack).

However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted

and has output an interrupt request to the CPU, the

IRQOUT pin holds low level.

Figure 6.3 Interrupt Sequence Flowchart

HD64F7047 Datasheet(PDF) 129 Page - Renesas Technology Corp

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