HD64F7047 datasheet(140/764 Pages) RENESAS

Part #	HD64F7047

Description	Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

PDF	764 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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140 / 764 page

Rev. 2.00, 09/04, page 100 of 720

7.2.4

User Break Control Register (UBCR)

The user break control register (UBCR) is a 16-bit readable/writable register that (1) enables or

disables user break interrupts and (2) sets the pulse width of the

UBCTRG signal output in the

event of a break condition match.

Bit

Bit Name

Initial

Value

R/W

Description

15 to 3



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

CKS1

CKS0

R/W

Clock Select 1 and 0

These bits specify the pulse width of the

UBCTRG

signal output in the event of a condition match.

00:

UBCTRG pulse width is φ

01:

UBCTRG pulse width is φ/4

10:

UBCTRG pulse width is φ/8

11:

UBCTRG pulse width is φ/16

Note:

φ means internal clock

UBID

R/W

User Break Disable

Enables or disables user break interrupt request

generation in the event of a user break condition

match.

0: User break interrupt request is enabled

1: User break interrupt request is disabled

HD64F7047 Datasheet(PDF) 140 Page - Renesas Technology Corp

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