HD64F7047 datasheet(141/764 Pages) RENESAS

141 / 764 page

Rev. 2.00, 09/04, page 101 of 720

7.3

Operation

7.3.1

Flow of the User Break Operation

The flow from setting of break conditions to user break interrupt exception processing is described

below:

1. The user break addresses are set in the user break address register (UBAR), the desired masked

bits in the addresses are set in the user break address mask register (UBAMR) and the breaking

bus cycle type is set in the user break bus cycle register (UBBR). If even one of the three

groups of the UBBR’s CPU cycle/DTC cycle select bits (CP1, CP0), instruction fetch/data

access select bits (ID1, ID0), and read/write select bits (RW1, RW0) is set to 00 (no user break

generated), no user break interrupt will be generated even if all other conditions are satisfied.

When using user break interrupts, always be certain to establish bit conditions for all of these

three groups.

2. The UBC uses the method shown in figure 7.2 to determine whether set conditions have been

satisfied or not. When the set conditions are satisfied, the UBC sends a user break interrupt

request signal to the interrupt controller (INTC). At the same time, a condition match signal is

output at the

UBCTRG pin with the pulse width set in bits CKS1 and CKS0.

3. The interrupt controller checks the accepted user break interrupt request signal’s priority level.

The user break interrupt has priority level 15, so it is accepted only if the interrupt mask level

in bits I3–I0 in the status register (SR) is 14 or lower. When the I3–I0 bit level is 15, the user

break interrupt cannot be accepted but it is held pending until user break interrupt exception

processing can be carried out. Consequently, user break interrupts within NMI exception

service routines cannot be accepted, since the I3–I0 bit level is 15. However, if the I3–I0 bit

level is changed to 14 or lower at the start of the NMI exception service routine, user break

interrupts become acceptable thereafter. See section 6, Interrupt Controller (INTC), for the

details on the handling of priority levels.

4. The INTC sends the user break interrupt request signal to the CPU, which begins user break

interrupt exception processing upon receipt. See section 6.6, Interrupt Operation, for the details

on interrupt exception processing.

HD64F7047 Datasheet(PDF) 141 Page - Renesas Technology Corp