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HD64F7047 Datasheet(PDF) 184 Page - Renesas Technology Corp

Part # HD64F7047
Description  Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series
PDF  764 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F7047 Datasheet(HTML) 184 Page - Renesas Technology Corp

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Rev. 2.00, 09/04, page 144 of 720
9.6.3
CS Assert Period Extension
Idle cycles can be inserted to prevent extension of the
RD or WRL signal assert period beyond the
length of the
CS0 signal assert period by setting the SW0 bit of BCR2. This allows for flexible
interfaces with external circuitry. The timing is shown in figure 9.6. T
h and Tf cycles are added
respectively before and after the normal cycle. Only
CS0 is asserted in these cycles; RD and WRL
signals are not. Further, data is extended up to the T
f cycle, which is effective for gate arrays and
the like, which have slower write operations.
Write
Data
WRL
Data
RD
CS0
Address
CK
Read
Th
T1
T2
Tf
Figure 9.6
CS Assert Period Extension Function



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