HD64F7047 datasheet(200/764 Pages) RENESAS

200 / 764 page

Rev. 2.00, 09/04, page 160 of 720

10.3.2

Timer Mode Register (TMDR)

The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of

each channel. The MTU has five TMDR registers, one for each channel. TMDR register settings

should be changed only when TCNT operation is stopped.

Bit

Bit Name

Initial

value

R/W

Description

7, 6



All 1



Reserved

These bits are always read as 1, and should only be

written with 1.

BFB

R/W

Buffer Operation B

Specifies whether TGRB is to operate in the normal way,

or TGRB and TGRD are to be used together for buffer

operation. When TGRD is used as a buffer register, TGRD

input capture/output compare is not generated.

In channels 1 and 2, which have no TGRD, bit 5 is

reserved. It is always read as 0, and should only be written

with 0.

0: TGRB and TGRD operate normally

1: TGRB and TGRD used together for buffer operation

BFA

R/W

Buffer Operation A

Specifies whether TGRA is to operate in the normal way,

or TGRA and TGRC are to be used together for buffer

operation. When TGRC is used as a buffer register, TGRC

input capture/output compare is not generated.

In channels 1 and 2, which have no TGRC, bit 4 is

reserved. It is always read as 0, and should only be written

with 0.

0: TGRA and TGRC operate normally

1: TGRA and TGRC used together for buffer operation

MD3

MD2

MD1

MD0

R/W

Modes 0 to 3

These bits are used to set the timer operating mode.

See table 10.9 for details.

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