HD64F7047 datasheet(202/764 Pages) RENESAS

202 / 764 page

Rev. 2.00, 09/04, page 162 of 720

10.3.3

Timer I/O Control Register (TIOR)

The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU

has eight TIOR registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2.

Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is

valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM

mode 2, the output at the point at which the counter is cleared to 0 is specified.

When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register

operates as a buffer register.

• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4

Bit

Bit Name

Initial

value

R/W

Description

IOB3

IOB2

IOB1

IOB0

R/W

I/O Control B0 to B3

Specify the function of TGRB.

See the following tables.

TIORH_0: Table 10.10

TIOR_1:

Table 10.14

TIOR_2:

Table 10.16

TIORH_3: Table 10.18

TIORH_4: Table 10.22

IOA3

IOA2

IOA1

IOA0

R/W

I/O Control A0 to A3

Specify the function of TGRA.

See the following tables.

TIORH_0: Table 10.11

TIOR_1:

Table 10.15

TIOR_2:

Table 10.17

TIORH_3: Table 10.19

TIORH_4: Table 10.23

HD64F7047 Datasheet(PDF) 202 Page - Renesas Technology Corp

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