HD64F7047 datasheet(281/764 Pages) RENESAS

281 / 764 page

Rev. 2.00, 09/04, page 241 of 720

10. Complementary PWM Mode 0% and 100% Duty Output

In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures

10.43 to 10.47 show output examples.

100% duty output is performed when the data register value is set to H'0000. The waveform in

this case has a positive phase with a 100% on-state. 0% duty output is performed when the data

phase with a 100% off-state.

On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn-

off compare-match for the same phase occur simultaneously, both compare-matches are

ignored and the waveform does not change.

11. Toggle Output Synchronized with PWM Cycle

In complementary PWM mode, toggle output can be performed in synchronization with the

PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR).

An example of a toggle output waveform is shown in Figure 10.48.

This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare-

match between TCNT4 and H'0000.

The output pin for this toggle output is the TIOC3A pin. The initial output is 1.

TGRA_3

H'0000

Toggle output

TIOC3A pin

TCNT_4

TCNT_3

Figure 10.48 Example of Toggle Output Waveform Synchronized with PWM Output

HD64F7047 Datasheet(PDF) 281 Page - Renesas Technology Corp