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HD64F7047 Datasheet(PDF) 282 Page - Renesas Technology Corp |
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HD64F7047 Datasheet(HTML) 282 Page - Renesas Technology Corp |
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282 / 764 page ![]() Rev. 2.00, 09/04, page 242 of 720 12. Counter Clearing by another Channel In complementary PWM mode, by setting a mode for synchronization with another channel by means of the timer synchro register (TSYR), and selecting synchronous clearing with bits CCLR2–CCLR0 in the timer control register (TCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by another channel. Figure 10.49 illustrates the operation. Use of this function enables counter clearing and restarting to be performed by means of an external signal. TGRA_3 TCDR TDDR H'0000 Channel 1 Input capture A TCNT_1 TCNT_3 TCNT_4 TCNTS Synchronous counter clearing by channel 1 input capture A Figure 10.49 Counter Clearing Synchronized with Another Channel |
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