HD64F7047 datasheet(286/764 Pages) RENESAS

286 / 764 page

Rev. 2.00, 09/04, page 246 of 720

Complementary PWM Mode Output Protection Function: Complementary PWM mode output

has the following protection functions.

1. Register and counter miswrite prevention function

With the exception of the buffer registers, which can be rewritten at any time, access by the

CPU can be enabled or disabled for the mode registers, control registers, compare registers,

and counters used in complementary PWM mode by means of bit 13 in the bus controller’s bus

control register 1 (BCR1). Some registers in channels 3 and 4 concerned are listed below: total

21 registers of TCR_3 and TCR_4; TMDR_3 and TMDR_4; TIORH_3 and TIORH_4;

TIORL_3 and TIORL_4; TIER_3 and TIER_4; TCNT_3 and TCNT_4; TGRA_3 and

TGRA_4; TGRB_3 and TGRB_4; TOER; TOCR; TGCR; TCDR; and TDDR. This function

enables the CPU to prevent miswriting due to the CPU runaway by disabling CPU access to

the mode registers, control register, and counters. In access disabled state, an undefined value

is read from the registers concerned, and cannot be modified.

2. Halting of PWM output by external signal

The 6-phase PWM output pins can be set automatically to the high-impedance state by

inputting specified external signals. There are four external signal input pins.

See section 10.9, Port Output Enable (POE), for details.

3. Halting of PWM output when oscillator is stopped

If it is detected that the clock input to this LSI has stopped, the 6-phase PWM output pins

automatically go to the high-impedance state. The pin states are not guaranteed when the clock

is restarted.

See section 4.2, Function for Detecting the Oscillator Halt, for details.

HD64F7047 Datasheet(PDF) 286 Page - Renesas Technology Corp