HD64F7047 datasheet(289/764 Pages) RENESAS

289 / 764 page

Rev. 2.00, 09/04, page 249 of 720

Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the

TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt

request is cleared by clearing the TCFV flag to 0. The MTU has five overflow interrupts, one for

each channel.

Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the

TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt

request is cleared by clearing the TCFU flag to 0. The MTU has four underflow interrupts, one

each for channels 1 and 2.

10.5.2

DTC Activation

The DTC can be activated by the TGR input capture/compare match interrupt in each channel. For

details, see section 8, Data Transfer Controller (DTC).

A total of 17 MTU input capture/compare match interrupts can be used as DTC activation sources,

four each for channels 0 and 3, and two each for channels 1 and 2, and five for channel 4.

10.5.3

A/D Converter Activation

The A/D converter can be activated by the TGRA input capture/compare match in each channel.

If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a

TGRA input capture/compare match on a particular channel, a request to start A/D conversion is

sent to the A/D converter. If the MTU conversion start trigger has been selected on the A/D

converter at this time, A/D conversion starts.

In the MTU, a total of five TGRA input capture/compare match interrupts can be used as A/D

converter conversion start sources, one for each channel.

HD64F7047 Datasheet(PDF) 289 Page - Renesas Technology Corp