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4502 Datasheet(PDF) 160 Page - Renesas Technology Corp

Part # 4502
Description  4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES
PDF  214 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

4502 Datasheet(HTML) 160 Page - Renesas Technology Corp

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2.7 RAM back-up
2-43
4502 Group
APPLICATION
Rev.2.01
Feb 02, 2005
REJ09B0193-0201
2.7 RAM back-up
2.7.1 RAM back-up mode
The system enters RAM back-up mode when the POF or POF2 instruction is executed after the EPOF
instruction is executed. Table 2.7.1 shows the function and state retained at RAM back-up mode. Also,
Table 2.7.2 shows the return source from this state.
(1)
RAM back-up mode
As oscillation stops with RAM, the state of reset circuit retained, current dissipation can be reduced
without losing the contents of RAM.
Table 2.7.1 Functions and states retained at RAM back-up mode
Notes 1: “O” represents that the function can be retained, and “✕” represents that the function is initialized.
Registers and flags other than the above are undefined at RAM back-up, and set an initial value
after returning.
2: The stack pointer (SP) points the level of the stack register and is initialized to “7” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer flag WDF1 with the WRST instruction, and then execute the POF or
POF2 instruction.
5: The voltage drop detection circuit is operating at the RAM back-up state and sytem reset occurs
when the voltage drop is detected.
6: As for the D2/C pin, the output latch of port C is set to “1” at the RAM back-up. However, the
output latch of port D2 is retained.
As for the other ports, their output levels are retained at the RAM back-up.
Function
Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Port level
Selected oscillation circuit
Timer control register W1
Timer control registers W2, W6
Clock control register MR
Interrupt control registers V1, V2
Interrupt control register I1
Timer 1 function
Timer 2 function
A/D function
Voltage drop detection circuit
Pull-up control registers PU0–PU2
Key-on wakeup control registers K0–K2
A/D control register Q1
External 0 interrupt request flag (EXF0)
Timer 1 interrupt request flag (T1F)
Timer 2 interrupt request flag (T2F)
A/D conversion completion flag (ADF)
Watchdog timer flags (WDF1)
Watchdog timer enable flag (WEF)
16-bit timer (WDT)
Interrupt enable flag (INTE)
POF
✕
O
(Note 6)
O
✕
O
✕
✕
O
✕
(Note 3)
✕
O (Note 5)
O
O
O
✕
✕
(Note 3)
✕
✕ (Note 4)
✕
✕ (Note 4)
✕
RAM back-up
POF2
✕
O
(Note 6)
O
✕
O
✕
✕
O
✕
(Note 3)
✕
✕
O
O
O
✕
✕
(Note 3)
✕
✕ (Note 4)
✕
✕ (Note 4)
✕



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