7906 datasheet(365/531 Pages) RENESAS

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DEBUG FUNCTION

7906 Group User’s Manual Rev.2.0

17-4

17.2.2 Debug control register 1

Figure 17.2.3 shows the structure of the debug control register 1.

Fig. 17.2.3 Structure of debug control register 1

(1) Address compare register access enable bit (bit 2)

Setting this bit to “1” enables reading from or writing to the contents of address compare registers 0

and 1 (addresses 6816 to 6D16), while clearing this bit to “0” disables this reading or writing.

Be sure to set this bit to “1” immediately before reading from or writing to the address compare

registers 0 and 1, and then clear it to “0” immediately after this reading or writing.

(2) Address-matching-detection 2 decision bit (bit 6)

When the address matching detection 2 is selected, this bit is used to decide which of the addresses

being set in the address compare registers 0 and 1 matches with the contents of PG and PC.

This bit is cleared to “0” when the contents of PG and PC matches with the address being set in

address compare register 0 and set to “1” when the contents of PG and PC match with the one being

set in the address compare register 1.

This bit is invalid when the address matching detection 0 and 1 are selected.

(Note 1)

Undefined

—

Bit name

Bit

Debug control register 1 (Address 6716)

Function

At reset

R/W

Fix this bit to “0.”

The value is “0” at reading.

Address compare register

access enable bit (Note 2)

Fix this bit to “1” when using the debug function.

Nothing is assigned.

While a debugger is not used, the value is “0” at reading.

While a debugger is used, the value is “1” at reading.

Address-matching-detection 2

decision bit

(Valid when the address match-

ing detection 2 is selected.)

The value is “0” at reading.

0 : Disabled.

1 : Enabled.

0 : Matches with the contents of the address com-

pare register 0.

1 : Matches with the contents of the address com-

pare register 1.

Notes 1: At power-on reset, each bit become “0”; at hardware reset or software reset, each bit retains the value immediately before reset.

2: Be sure to set this bit to “1” immediately before the access to the address compare registers 0 and 1 (addresses 6816 to

6D16). Then, be sure to clear this bit to “0” immediately after this access.

b7 b6 b5 b4 b3 b2 b1 b0

17.2 Block description

(2) Detect enable bit (bit 5)

If any selected condition is satisfied when this bit = “1,” an address matching detection interrupt

request occurs.

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