7906 datasheet(367/531 Pages) RENESAS

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DEBUG FUNCTION

7906 Group User’s Manual Rev.2.0

17-6

17.3 Address matching detection mode

When the contents of PG and PC match with the specified address, an address matching detection interrupt

request occurs.

17.3.1 Setting procedure for address matching detection mode

Figure 17.3.1 shows an initial setting example for registers relevant to the address matching detection

mode.

Fig. 17.3.1 Initial setting example for registers relevant to address matching detection mode

Selection of detect condition

Debug control register 0 (Address 6616)

0 0 1 : Address matching detection 0

0 1 0 : Address matching detection 1

0 1 1 : Address matching detection 2

b1 b0

Detect enable bit

0 : Detection disabled.

Detect condition select bits

Detection starts.

Processing for setting of address compare registers

Debug control register 1 (Address 6716)

Address compare register access enable bit

(Note 1)

1 : Enabled.

b23

b0 Address compare register 0

(Addresses 6A16 to 6816)

Address compare register 1

(Addresses 6D16 to 6B16)

The address to be detected is set here.

Setting of address compare registers

Debug control register 1 (Address 6716)

Address compare register access enable bit

(Note 1)

0 : Disabled.

Set the detect enable bit to “1.”

Debug control register 0 (Address 6616)

Detect enable bit

1 : Detection enabled.

Disables interrupts.

The interrupt disable flag (I) is set to “1.”

Clear the interrupt disable flag (I) to “0” (Note 2).

Notes 1: Be sure to set this bit to “1” immediately before reading from or

writing to the address compare registers 0, 1. Then, be sure to

clear this bit to “0” immediately after this reading or writing.

2: This processing is unnecessary when no maskable interrupt is

used.

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