7906 datasheet(370/531 Pages) RENESAS

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DEBUG FUNCTION

7906 Group User’s Manual Rev.2.0

17-9

17.3 Address matching detection mode

Fig. 17.3.3 Example of ROM correct processing using address matching detection mode (2)

Address matching

detection interrupt routine

s Address matching detection 2 selected

Main routine

Defective

Former program ➀

TOP_BUG1

TOP_RTN1

Modified

Updated program ➀

The contents of PG and PC

saved onto the stack area

(address TOP_BUG1) are

rewritten to address

TOP_RTN1 (Note 2).

RTI

TOP_BUG1 : The start address of defective or former program ➀.

→This address is to be set in the address compare register 0, in advance.

TOP_RTN1 : The address next to the defective or former program ➀.

TOP_BUG2 : The start address of defective or former program ➁.

→This address is to be set in the address compare register 1, in advance.

TOP_RTN2 : The address next to the defective or former program ➁.

Notes 1: When an address matching detection interrupt request has been accepted, the interrupt

disable flag (I) is set to “1.” If another interrupt requests is required to be accepted under

the same conditions as those of the defective or former program, be sure to clear the

interrupt disable flag (I) to “0” at the start of an address matching detection interrupt

routine.

2: Each status of PG, PC, and PS immediately before acceptance of an address matching

detection interrupt request is saved onto the stack area. (The contents of PG, PC, and

PS are saved onto the stack area in this order.) Refer to section “6.7 Sequence from

acceptance of interrupt request until execution of interrupt routine.”

3: Make sure that this instruction is executed in the absolute long addressing mode. The

above is just an example. In an actual programming, be sure to refer to the format of the

assembler description to be used.

Defective

Former program ➁

TOP_BUG2

TOP_RTN2

Address-matching-

detection 2 decision bit?

Modified

Updated program ➁

The contents of PG and PC

saved onto the stack area

(address TOP_BUG2) are

rewritten to address

TOP_RTN2 (Note 2).

The interrupt disable flag (I)

is cleared to “0” (Note 1)

STAB A, LG : 0h (Note 3)

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