7906 datasheet(436/531 Pages) RENESAS

436 / 531 page

7906 Group User’s Manual Rev.2.0

20-31

APPENDIX

Appendix 2. Control registers

7 to 2

(Note)

Bit name

Bit

Particular function select register 0 (Address 6216)

Function

At reset

R/W

STP instruction invalidity select bit

External clcok input select bit

Fix these bits to “000000.”

b7 b6 b5 b4 b3 b2 b1 b0

0 : STP instruction is valid.

1 : STP instruction is invalid.

0 : Oscillation circuit is active. (Oscillator is connected.)

Watchdog timer is used at stop mode termination.

1 : Oscillation circuit is inactive. (External clock is

input.)

When the system clock select bit (bit 5 at address BC16) = “0,”

watchdog timer is not used at stop mode termination.

When the system clock select bit = “1,”

watchdog timer is used at stop mode termination.

Note: Writing to these bits requires the following procedure:

• Write “5516” to this register. (The bit status does not change only by this writing.)

• Succeedingly, write “0” or “1” to each bit.

Also, use the MOVMB (MOVM when m = 1) instruction or STAB (STA when m = 1) instruction.

If an interrupt occurs between writing of “5516” and next writing of “0” or “1,” latter writing may be ignored. When there is a

possibility that an interrupt occurs at the above timing, be sure to read this bit’s contents after writing of “0” or “1,” and verify

whether “0” or “1” has correctly been written or not.

(Note 2)

—

Notes 1: At power-on reset, this bit becomes “0.” At hardware reset or software reset, this bit retains the value just before reset.

2: Even when “1” is written, the bit status will not change.

3: Setting this bit to “1” must be performed just before execution of the WIT instruction. Also, after the wait state is termi-

nated, this bit must be cleared to “0” immediately.

(Note 1)

Particular function select register 1 (Address 6316)

b7 b6 b5 b4 b3 b2 b1 b0

Bit name

Bit

Function

At reset

R/W

STP-instruction-execution

status bit

WIT-instruction-execution

status bit

Fix this bit to “0.”

System clock stop select bit

at WIT

(Note 3)

Fix this bit to “0.”

The value is “0” at reading.

Timer B2 clock source select bit

(Valid in event counter mode.)

The value is “0” at reading.

0 : Normal operation.

1 : During execution of STP instruction

0 : Normal operation.

1 : During execution of WIT instruction

0 : External signal input to the TB2IN pin is counted.

1 : fX32 is counted.

0 : In the wait mode, system clock fsys is active.

1 : In the wait mode, system clock fsys is inactive.

Reference

15-4

4-10

15-5

16-4

Reference

15-6

16-5

8-15

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