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TIMER A

7906 Group User’s Manual Rev.2.0

7-23

7.4.2 Operation in event counter mode

➀ When the count start bit is set to “1,” the counter starts counting of the count source’s valid edge.

➁ When a counter underflow or overflow occurs, the reload register’s contents are reloaded, and counting

continues.

➂ The timer Aj interrupt request bit is set to “1” at the underflow or overflow in ➁.

The interrupt request bit remains set to “1” until the interrupt request is accepted or until the interrupt

request bit is cleared to “0” by software.

Figure 7.4.4 shows an example of operation in the event counter mode.

7.4 Event counter mode

Fig. 7.4.4 Example of operation in event counter mode (without pulse output and two-phase pulse

signal processing functions)

Timer Aj interrupt

request bit

FFFF16

000016

Time

Count start bit

Cleared to “0” when interrupt request is accepted or cleared by software.

Set to “1” by software.

Starts counting.

Up-down bit

Note: The above applies when the up-down bit’s contents are selected as the up-down switching factor (i.e., up-down

switching factor select bit = “0” ).

Set to “1” by software.

n : Reload register’s contents

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