7906 datasheet(279/531 Pages) RENESAS

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SERIAL I/O

7906 Group User’s Manual Rev.2.0

11-38

11.4 Clock asynchronous serial I/O (UART) mode

Error-permitted range of transfer baud

During reception, the receive data input to the RxDi pin is taken at the rising edge of the transfer

clock. (Refer to section “11.4.6 Receive operation.”) Accordingly, in order to receive data correctly,

the stop bit must be input when the transfer clock of one-set receive data rises last. Figure 11.4.1

shows the relationship between the transfer clock and receive data.

Fig. 11.4.1 Relationship between transfer clock and receive data

<1ST-8DATA-1SP>

At the falling edge of ST, the transfer clock is

generated, and reception starts.

When the transfer rate of

the receive data is faster

than the rate of the transfer

clock on the receiver side

When the transfer rate of

the receive data is slower

than the rate of the transfer

clock on the receiver side

RxDi

(Receive data)

Transfer clock

(Receiver side)

1 clock

8 clocks

1 clock

9.5 clocks

ST : Start bit

SP : Stop bit

✻ 1 period of BRGi’s count source (Maximum)

According to the condition of the input timing,

a maximum of this period (✻) can be omitted.

✻

SP must be detected at

this last rising edge of

the transfer clock.

Accordingly, the transfer rate of the receiver and transmitter sides must satisfy the following formula

in order to receive data correctly.

Br: Transfer rate on receiver side (bps)

Bt: Transfer rate on transmitter side (bps)

F : BRGi’s count source frequency on receiver side (Hz)

b : Entire bit number of one-set data

(ex: 12 bits in the case of 1ST-8DATA-1PAR-2SP; See Figure 11.4.2.)

✕ (b – 1) +

✕ (b – 0.5) +

✕ b

Be sure to satisfy the above formula, and set the timing with enough margin. Also, the user shall

make sufficient evaluation before actually using it.

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