32172 datasheet(73/875 Pages) RENESAS

73 / 875 page

3-14

Rev.1.0

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

D7 D8

D15

DMA0-4 Interrupt Mask Register (DM04ITMK)

DMA0 Channel Control Register (DM0CNT)

DMA0 Transfer Count Register (DM0TCT)

DMA0 Source Address Register (DM0SA)

DMA0 Destination Address Register (DM0DA)

DMA1 Channel Control Register (DM1CNT)

DMA1 Transfer Count Register (DM1TCT)

DMA1 Source Address Register (DM1SA)

DMA1 Destination Address Register (DM1DA)

H’0080 0412

H’0080 0414

H’0080 0416

H’0080 0418

H’0080 041A

H’0080 041C

H’0080 0410

H’0080 041E

H’0080 0422

H’0080 0424

H’0080 0426

H’0080 0428

H’0080 0420

DMA0-4 Interrupt Request Status Register (DM04ITST)

H’0080 0400

H’0080 0408

DMA5-9 Interrupt Mask Register (DM59ITMK)

DMA5-9 Interrupt Request Status Register (DM59ITST)

DMA5 Channel Control Register (DM5CNT)

DMA5 Transfer Count Register (DM5TCT)

DMA5 Source Address Register (DM5SA)

DMA5 Destination Address Register (DM5DA)

DMA6 Channel Control Register (DM6CNT)

DMA6 Transfer Count Register (DM6TCT)

H’0080 042A

H’0080 042C

H’0080 042E

DMA6 Source Address Register (DM6SA)

DMA6 Destination Address Register (DM6DA)

DMA0 Request Cause Extension Register (DM0REQ)

DMA5 Request Cause Extension Register (DM5REQ)

DMA1 Request Cause Extension Register (DM1REQ)

DMA6 Request Cause Extension Register (DM6REQ)

+0 address

+1 address

Address

Blank areas are reserved for future use.

Figure 3.4.6 Register Mapping of the SFR Area (3)

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