32172 datasheet(89/875 Pages) RENESAS

89 / 875 page

3-30

Rev.1.0

D7 D8

D15

H’0080 1808

TPD Counter (TPDCT)

TPD Measurement Register 0 (TPDMR0)

H’0080 180E

H’0080 1810

H’0080 1812

H’0080 1814

H’0080 1816

H’0080 181A

H’0080 181C

H’0080 181E

H’0080 1830

H’0080 1832

H’0080 1840

H’0080 1842

H’0080 1844

H’0080 1846

H’0080 184C

PD Calculation Interrupt Control Register (PDICR)

Position Detection Accuracy Select Register (PDASR)

Prescaler Register 0C(PRS0C)

H’0080 184E

H’0080 1860

H’0080 1862

H’0080 1864

H’0080 1866

SMSB Control Register 0 (SMSBCR0)

ABD0 Compare Register (ABD0CM)

PNEWLT0 Register (PNEWLT0)

H’0080 186E

H’0080 1872

H’0080 1876

H’0080 1878

H’0080 187A

H’0080 1800

H’0080 1806

H’0080 1802

H’0080 1804

H’0080 1818

H’0080184A

H’0080 186A

H’0080 186C

H’0080 1874

Prescaler Register B (PRSB)

TIN Input Processing Control Register (TINPDCR)

TIN Interrupt Control Register (TINPDICR)

TIN Interrupt Status Register (TINPDIST)

TPD Control Register (TPDCR)

TPD Measurement Register 1 (TPDMR1)

TPD Measurement Register 2 (TPDMR2)

TPD Measurement Register 3 (TPDMR3)

TPD Measurement Register 4 (TPDMR4)

TPD Measurement Register 5 (TPDMR5)

TPD Measurement Register 6 (TPDMR6)

TPD Measurement Register 7 (TPDMR7)

H’0080 1848

H’0080 1870

H’0080 1868

PD Calculation Interrupt Status Register (PDIST)

TEP0P Control Register (TEP0PCR)

TEP0M Control Register (TEP0MCR)

TEP0P Counter (TEP0PCT)

TEP0M Counter (TEP0MCT)

PD0 Data Update Disable Event Select Register (PDNSEL0R)

AB0 Mask Register (ABD0MK)

PICH0 Compare Register (PITCH0CMR)

POLDLT0 Register (POLDLT0)

MOLDLT0 Register (MOLDLT0)

MNEWLT0 Register (MNEWLT0)

PSUBLT0 Register (PSUBLT0)

MSUBLT0 Register (MSUBLT0)

PRLT0 Register (PRLT0)

SNEWLT0 Register (SNEWLT0)

MRLT0 Register (MRLT0)

FDLT0 Register (FDLT0)

ABDLT0 Register (ABDLT0)

PITCHLT0 Register (PITCHLT0)

RSUMLT0 Register (RSUMLT0)

SSLT0 Register (SSLT0)

PD0 Data Update Control Register (PDNCNT0R)

S Error 0 Detection Range Select Register (SNEW0MK)

DMA Transfer Request Cause Select Register (DMAREQSL)

Note: Enclosed in

are the intermediate registers used for arithmetic operations.

Do not access these registers for read/write.

Prescaler Register A (PRSA)

DACNT Reload Register A (DACNTRL)

DACNT Control Register A (DACNTCR)

DACNT Counter (DACNT)

+0 address

+1 address

Address

Blank areas are reserved for future use.

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

Figure 3.4.22 Register Mapping of the SFR Area (19)

32172 Datasheet(PDF) 89 Page - Renesas Technology Corp

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