32172 datasheet(77/875 Pages) RENESAS

77 / 875 page

3-18

Rev.1.0

ADDRESS SPACE

3.4 Internal RAM and SFR Areas

H'0080 0A10

H'0080 0A12

H'0080 0A30

H'0080 0A32

H'0080 0A36

H'0080 0A40

H'0080 0A42

H'0080 0A44

H'0080 0A46

H'0080 0A80

H'0080 0A82

H'0080 0A84

H'0080 0A86

H'0080 0A8E

D7 D8

D15

H'0080 0A8A

H'0080 0A90

H'0080 0A94

H'0080 0A96

H'0080 0A98

H'0080 0A9A

H'0080 0A9E

H'0080 0AA0

H'0080 0AA2

H'0080 0AA4

H'0080 0AA6

H'0080 0AA8

H'0080 0AAC

H'0080 0AAE

H'0080 0A16

H'0080 0A14

H'0080 0A8C

H'0080 0A00

SIO67 Interrupt Status Register (SI67STAT)

SIO47 Interrupt Mask Register (SI47MASK)

H'0080 0A02

H'0080 0A20

H'0080 0A22

H'0080 0A24

H'0080 0A26

H'0080 0A34

SIO47 Receive Interrupt Cause Select Register (SI47SEL)

SIO4 Transmit Control Register (S4TCNT)

SIO4 Transmit/Receive Mode Register (S4MOD)

SIO4 Transmit Buffer Register (S4TXB)

SIO4 Receive Buffer Register (S4RXB)

SIO4 Receive Control Register (S4RCNT)

SIO4 Baud Rate Register (S4BAUR)

SIO5 Transmit Control Register (S5TCNT)

SIO5 Transmit/Receive Mode Register (S5MOD)

SIO5 Transmit Buffer Register (S5TXB)

SIO5 Receive Buffer Register (S5RXB)

SIO5 Receive Control Register (S5RCNT)

SIO5 Baud Rate Register (S5BAUR)

SIO6 Transmit Control Register (S6TCNT)

SIO6 Transmit/Receive Mode Register (S6MOD)

SIO6 Transmit Buffer Register (S6TXB)

SIO6 Receive Buffer Register (S6RXB)

SIO6 Receive Control Register (S6RCNT)

SIO6 Baud Rate Register (S6BAUR)

SIO7 Transmit Control Register (S7TCNT)

SIO7 Transmit/Receive Mode Register (S7MOD)

SIO7 Transmit Buffer Register (S7TXB)

SIO7 Receive Buffer Register (S7RXB)

SIO7 Receive Control Register (S7RCNT)

SIO7 Baud Rate Register (S7BAUR)

H'0080 0A88

H'0080 0A92

H'0080 0A9C

H'0080 0AAA

A-D1 Single Mode Register 0 (AD1SIM0)

A-D1 Single Mode Register 1 (AD1SIM1)

A-D1 Scan Mode Register 0 (AD1SCM0)

A-D1 Scan Mode Register 1(AD1SCM1)

A-D1 Conversion Rate Control Register (AD1CVCR)

A-D1 Successive Approximation Register (AD1SAR)

A-D1 Comparate Data Register (AD1CMP)

A-D1 Digital Input Control Register (AD1CHCON)

10-bit A-D1 Data Register 0 (AD1DT0)

10-bit A-D1 Data Register 1 (AD1DT1)

10-bit A-D1 Data Register 2 (AD1DT2)

10-bit A-D1 Data Register 3 (AD1DT3)

10-bit A-D1 Data Register 4 (AD1DT4)

10-bit A-D1 Data Register 5 (AD1DT5)

10-bit A-D1 Data Register 6 (AD1DT6)

10-bit A-D1 Data Register 7 (AD1DT7)

10-bit A-D1 Data Register 8 (AD1DT8)

10-bit A-D1 Data Register 9 (AD1DT9)

10-bit A-D1 Data Register 10 (AD1DT10)

10-bit A-D1 Data Register 11 (AD1DT11)

10-bit A-D1 Data Register 12 (AD1DT12)

10-bit A-D1 Data Register 13 (AD1DT13)

10-bit A-D1 Data Register 14 (AD1DT14)

10-bit A-D1 Data Register 15 (AD1DT15)

+0 address

+1 address

Address

Blank areas are reserved for future use.

Figure 3.4.10 Register Mapping of the SFR Area (7)

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