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32172 Datasheet(PDF) 29 Page - Renesas Technology Corp |
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32172 Datasheet(HTML) 29 Page - Renesas Technology Corp |
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29 / 875 page ![]() 1 1-8 Rev.1.0 Table 1.2.1 Features of the M32R Family CPU Core Functional Block Features M32R family • Bus specifications CPU core Basic bus cycle: 25 ns (when CPU clock = 40 MHz) Logical address space: 4 Gbytes linear External extended area: Maximum 4 Mbytes External data bus: 16 bits • Implementation: Five-stage pipelined processing • CPU core internally configured in 32 bits • Register configuration General-purpose register: 32 bits x 16 Control register: 32 bits x 5 • Instruction set 16-bit/32-bit instruction formats 83 discrete instructions/6 addressing modes • Built-in multiplier-accumulator (32 x 16 + 56) Table 1.2.2 Features of the Internal Memory Functional Block Features RAM • Capacity M32172F2: 16 Kbytes M32173F2: 32 Kbytes • No-wait access • By using the RTD (Real-time Debugger), the internal RAM can be accessed for data read or rewrite from the outside, independently of the M32R. Flash memory • Capacity: 256 Kbytes • No-wait access • Durability: Can be rewritten 100 times Overview 1.2 Block Diagram |
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