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32172 Datasheet(PDF) 28 Page - Renesas Technology Corp |
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32172 Datasheet(HTML) 28 Page - Renesas Technology Corp |
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28 / 875 page  1 1-7 Rev.1.0 Figure 1.2.1 Block Diagram Overview 1.2 Block Diagram 1.2 Block Diagram Figure 1.2.1 shows a block diagram of the 32172/32173. The features of each block are outlined in Tables 1.2.1 to 1.2.3. 32172 PLL Clock Generating Circuit Internal Bus Interface Address Data Internal RAM (M32172F2 : 16KB) Internal Flash Memory (256KB) M32R CPU Core (max 40MHz) Multiplier- accumulator DMAC (10 channels) Input/output Timer (26 channels) Serial I/O (8 channels) A-D Converter x 2 (A-D0: 10-bit A-D, 8 channels) (A-D1: 10-bit A-D, 4 channels) Wait Controller Interrupt Controller (interrupt sources in 8 levels) Real-time Debugger (RTD) External Bus Interface Input/output Ports (JTAG), 99 lines Full CAN (2 channels) D-A Converter x 2 (8 bits) PD Controller (M32173F2 : 32KB) 32173 (32 x 16+56) |
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