32172 datasheet(18/875 Pages) RENESAS

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CHAPTER 19 RAM BACKUP MODE

19.1 Outline ................................................................................................................. 19-2

19.2 Example of RAM Backup when Power is Down .................................................. 19-2

19.2.1 Normal Operating State .................................................................... 19-3

19.2.2 RAM Backup State ........................................................................... 19-4

19.3 Example of RAM Backup for Saving Power Consumption .................................. 19-5

19.3.1 Normal Operating State .................................................................... 19-6

19.3.2 RAM Backup State ........................................................................... 19-7

19.3.3 Precautions to Be Observed at Power-on ........................................ 19-8

19.4 Exiting RAM Backup Mode (Wakeup) ................................................................. 19-9

CHAPTER 20 OSCILLATION CIRCUIT

20.1 Oscillator Circuit ................................................................................................... 20-2

20.1.1 Example of an Oscillator Circuit ........................................................... 20-2

20.1.2 System Clock Output Function ............................................................. 20-3

20.1.3 Oscillation Stabilization Time at Power-on ........................................... 20-4

20.2 Clock Generator Circuit ....................................................................................... 20-5

CHAPTER 21 JTAG

21.1 Outline of the JTAG ............................................................................................. 21-2

21.2 Configuration of the JTAG Circuit ........................................................................ 21-3

21.3 JTAG Registers ................................................................................................... 21-4

21.3.1 Instruction Register (JTAGIR) .......................................................... 21-4

21.3.2 Data Registers .................................................................................. 21-5

21.4 Basic Operation of the JTAG ............................................................................... 21-6

21.4.1 Outline of the JTAG Operation ......................................................... 21-6

21.4.2 IR Path Sequence ............................................................................ 21-8

21.4.3 DR Path Sequence ........................................................................... 21-10

21.4.4 Examining and Setting Data Registers ............................................. 21-12

21.5 Boundary Scan Description Language ................................................................ 21-14

21.6 Precautions on Board Design when Connecting the JTAG ................................. 21-37

21.7 Processing Pins when Not Using the JTAG ........................................................ 21-39

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