32172 datasheet(23/875 Pages) RENESAS

23 / 875 page

1-2

Rev.1.0

1.1 Overview

1.1.1 M32R Family CPU Core

(1) Uses the RISC architecture

• The 32172/32173 are 32-bit, RISC single-chip microcomputers built around the M32R family

CPU core (hereafter referred to as the "M32R") and incorporating flash memory, RAM, and

various other peripheral functions... all integrated into a single chip.

• The M32R uses the RISC architecture. Memory accesses are performed using Load and Store

instructions, and various arithmetic operations are executed using register-to-register

operating instructions. The M32R internally has sixteen 32-bit general-purpose registers and a

total of 83 discrete instructions.

• In addition to Load and Store instructions, the M32R supports compound instructions such as

Load & Address Update and Store & Address Update. These instructions are useful for

speeding up data transfers.

(2) 5-stage pipelined processing

• The M32R uses 5-stage pipelined instruction processing consisting of Instruction Fetch,

Decode, Execute, Memory Access, and Write Back. Not just load and store instructions or

Update and Store & Address Update also are executed in one cycle.

• Instructions are entered into the execution stage in the order they are fetched, but this does not

always mean that the first instruction entered is executed first. If the execution of a load or store

instruction entered earlier is delayed by one or more wait cycles inserted in memory access, a

store instruction. By using "out-of-order-completion" like this, the M32R controls instruction

execution without wasting clock cycles.

(3) Compact instruction code

• Instructions of the M32R come in either a 16-bit instruction or a 32-bit instruction format. Use of

the 16-bit instruction format especially helps to reduce the code size of a program.

• Some 32-bit instructions can branch directly to a location 32 Mbytes forward or backward from

the currently executed instruction address. The availability of such instructions makes

programming easier than for architectures with segmented address spaces.

Overview

1.1 Overview

32172 Datasheet(PDF) 23 Page - Renesas Technology Corp