ATmega32U2 datasheet(183/314 Pages) ATMEL

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7799B–AVR–07/09

ATmega8U2/16U2/32U2

19.7.4

UCSRnC – USART MSPIM Control and Status Register n C

• Bit 7:6 - UMSELn[1:0]: USART Mode Select

These bits select the mode of operation of the USART as shown in Table 19-3. See “UCSRnC –

USART Control and Status Register n C” on page 169 for full description of the normal USART

operation. The MSPIM is enabled when both UMSELn bits are set to one. The UDORDn,

UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM is enabled.

• Bit 5:3 - Reserved Bits in MSPI mode

When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,

these bits must be written to zero when UCSRnC is written.

• Bit 2 - UDORDn: Data Order

When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the

data word is transmitted first. Refer to the Frame Formats section page 4 for details.

• Bit 1 - UCPHAn: Clock Phase

The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last)

edge of XCKn. Refer to the SPI Data Modes and Timing section page 4 for details.

• Bit 0 - UCPOLn: Clock Polarity

The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and

UCPHAn bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and

Timing section page 4 for details.

19.7.5

UBRRnL and UBRRnH – USART MSPIM Baud Rate Registers

The function and bit description of the baud rate registers in MSPI mode is identical to normal

USART operation. See “UBRRnL and UBRRnH – USART Baud Rate Registers” on page 171.

19.8

AVR USART MSPIM vs. AVR SPI

The USART in MSPIM mode is fully compatible with the AVR SPI regarding:

• Master mode timing diagram.

• The UCPOLn bit functionality is identical to the SPI CPOL bit.

• The UCPHAn bit functionality is identical to the SPI CPHA bit.

• The UDORDn bit functionality is identical to the SPI DORD bit.

Bit

543

UMSELn1

UMSELn0

–

UDORDn

UCPHAn

UCPOLn

UCSRnC

Read/Write

R/W

Initial Value

Table 19-3.

UMSELn Bits Settings

UMSELn1

UMSELn0

Mode

Asynchronous USART

Synchronous USART

(Reserved)

Master SPI (MSPIM)

ATmega32U2 Datasheet(PDF) 183 Page - ATMEL Corporation

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