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ST7735 Datasheet(PDF) 22 Page - Sitronix Technology Co., Ltd. |
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ST7735 Datasheet(HTML) 22 Page - Sitronix Technology Co., Ltd. |
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22 / 166 page ![]() ST7735 V1.7 22 2009-12-04 TDST Data setup time 10 ns TDHT Data hold time 10 ns TRAT Read access time (ID) 40 ns TRATFM Read access time (FM) 40 ns D[17:0] TODH Output disable time 80 ns For CL=30pF Table 8.1.1 Parallel Interface Characteristics Note: VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=DGND=0V, Ta=25 ℃ V IH=0.7 x VDDI V IL=0.3 x VDDI T R T R=TF<=15ns V OH=0.8 x VDDI V OL=0.2 x VDDI T R T R=TF<=15ns T F T F Fig. 8.1.2 Rising and falling timing for input and output signal Fig. 8.1.3 Chip selection (CSX) timing Fig. 8.1.4 Write-to-read and read-to-write timing Note: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. |
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