ST7735 datasheet(23/166 Pages) SITRONIX

23 / 166 page

ST7735

V1.7

2009-12-04

8.2 Serial interface characteristics (3-line serial)

CSX

VIH

VIL

TCHW

TCSH

TOH

TCSS

SCL

SDA

(DOUT)

TSCC

TSCYCW/TSCYCR

TACC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

TSDS

TSDH

TSHW/TSHR

TSLW/TSLR

Fig. 8.2.1 3-line serial interface timing

Signal

Symbol

Parameter

Min

Max

Unit

Description

TCSS

Chip select setup time (write)

TCSH

Chip select hold time (write)

TCSS

Chip select setup time (read)

TSCC

Chip select hold time (read)

CSX

TCHW

Chip select “H” pulse width

TSCYCW

Serial clock cycle (Write)

TSHW

SCL “H” pulse width (Write)

TSLW

SCL “L” pulse width (Write)

TSCYCR

Serial clock cycle (Read)

150

TSHR

SCL “H” pulse width (Read)

SCL

TSLR

SCL “L” pulse width (Read)

TSDS

Data setup time

TSDH

Data hold time

TACC

Access time

SDA

(DIN)

(DOUT)

TOH

Output disable time

For maximum CL=30pF

For minimum CL=8pF

Table 8.2.1 3-line Serial Interface Characteristics

Note 1: VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=DGND=0V, Ta=25 ℃

Note 2: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30%

and 70% of VDDI for Input signals.

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