LPC3131 datasheet(18/68 Pages) NXP

18 / 68 page

LPC3130_3131_1

Preliminary data sheet

Rev. 1 — 9 February 2009

18 of 68

NXP Semiconductors

LPC3130/3131

Low-cost, low-power ARM926EJ-S microcontrollers

6.8 Internal RAM memory

The ISRAM (Internal Static RAM Memory) controller module is used as controller

between the AHB bus and the internal RAM memory. The internal RAM memory can be

used as working memory for the ARM processor and as temporary storage to execute the

code that is loaded by boot ROM from external devices such as SPI-ﬂash, NAND ﬂash,

and SD/MMC cards.

This module has the following features:

• Capacity of 96 kB (LPC3130) or 192 kB (LPC3131)

• On LPC3131 implemented as two independent 96 kB memory banks

6.9 Memory Card Interface (MCI)

The MCI controller interface can be used to access memory cards according to the

Secure Digital (SD) and Multi-Media Card (MMC) standards. The host controller can be

used to interface to small form factor expansion cards compliant to the SDIO card

standard as well. Finally, the MCI supports CE-ATA 1.1 compliant hard disk drives.

This module has the following features:

• One 8-bit wide interface.

• Supports high-speed SD, versions 1.01, 1.10 and 2.0.

• Supports SDIO version 1.10.

• Supports MMCplus, MMCmobile and MMCmicro cards based on MMC 4.1.

• Supports SDHC memory cards.

• CRC generation and checking.

Table 8.

LPC3130/3131 boot modes

Boot mode

GPIO0 GPIO1 GPIO2 Description

NAND

Boots from NAND ﬂash. If proper image is not found,

boot ROM will switch to DFU boot mode.

SPI

Boot from SPI NOR ﬂash connected to SPI_CS_OUT0. If

proper image is not found, boot ROM will switch to DFU

boot mode.

DFU

Device boots via USB using DFU class speciﬁcation.

SD/MMC

Boot ROM searches all the partitions on the

SD/MMC/SDHC/MMC+/eMMC/eSD card for boot image.

If partition table is missing, it will start searching from

sector 0. A valid image is said to be found if a valid image

header is found, followed by a valid image. If a proper

image is not found, boot ROM will switch to DFU boot

mode.

Reserved 0

Reserved for testing.

NOR ﬂash

Boot from parallel NOR ﬂash connected to

EBI_NSTCS_1.

UART

Boot ROM tries to download boot image from UART

((115200 – 8 – n -1) assuming 12 MHz FFAST clock).

Test

Boot ROM is testing ISRAM using memory pattern test.

After test switches to UART boot mode.

LPC3131 Datasheet(PDF) 18 Page - NXP Semiconductors

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