LPC3131 datasheet(20/68 Pages) NXP

20 / 68 page

LPC3130_3131_1

Preliminary data sheet

Rev. 1 — 9 February 2009

20 of 68

NXP Semiconductors

LPC3130/3131

Low-cost, low-power ARM926EJ-S microcontrollers

– Data is transferred from incrementing memory to a ﬁxed address of a peripheral.

The ﬂow is controlled by the peripheral.

Peripheral to memory:

– Data is transferred from a ﬁxed address of a peripheral to incrementing memory.

The ﬂow is controlled by the peripheral.

• Supports single data transfers for all transfer types.

• Supports burst transfers for memory to memory transfers. A burst always consists of

multiples of 4 (32 bit) words.

• The DMA controller has 12 channels.

• Scatter-gather is used to gather data located at different areas of memory. Two

channels are needed per scatter-gather action.

• Supports byte, half word and word transfers, and correctly aligns it over the AHB bus.

• Compatible with ARM ﬂow control for single requests (sreq), last single requests

(lsreq), terminal count info (tc), and dma clearing (clr).

• Supports swapping in endianess of the transported data.

6.12 Interrupt controller (INTC)

The interrupt controller collects interrupt requests from multiple devices, masks interrupt

requests, and forwards the combined requests to the processor. The interrupt controller

also provides facilities to identify the interrupt requesting devices to be served.

This module has the following features:

• The interrupt controller decodes all the interrupt requests issued by the on-chip

peripherals.

• Two interrupt lines (Fast Interrupt Request (FIQ), Interrupt Request (IRQ)) to the ARM

core. The ARM core supports two distinct levels of priority on all interrupt sources,

FIQ for high priority interrupts and IRQ for normal priority interrupts.

• Software interrupt request capability associated with each request input.

• Visibility of the interrupt’s request state before masking.

• Support for nesting of interrupt service routines.

• Interrupts routed to IRQ and to FIQ are vectored.

Table 9:

Peripherals that support DMA access

Peripheral name

Supported Transfer Types

NAND ﬂash controller

Memory to memory

SPI