LPC3131 datasheet(16/68 Pages) NXP

16 / 68 page

LPC3130_3131_1

Preliminary data sheet

Rev. 1 — 9 February 2009

16 of 68

NXP Semiconductors

LPC3130/3131

Low-cost, low-power ARM926EJ-S microcontrollers

• Software control mode where the ARM is directly master of the ﬂash device.

• Support for 8 bit and 16 bit ﬂash devices.

• Support for any page size from 0.5 kB upwards.

• Programmable NAND ﬂash timing parameters.

• Support for up to 4 NAND devices.

• Error Correction Module (ECC) for MLC NAND ﬂash support:

– Reed-Solomon error correction encoding and decoding.

– Uses Reed-Solomon code words with 9-bit symbols over GF(29), a total codeword

length of 469 symbols, including 10 parity symbols, giving a minimum Hamming

distance of 11.

– Up to 8 symbol errors can be corrected per codeword.

– Error correction can be turned on and off to match the demands of the application.

– Parity generator for error correction encoding.

– Wear leveling information can be integrated into protected data.

– Interrupts generated after completion of error correction task with 3 interrupt

registers.

– Error correction statistics distributed to ARM using interrupt scheme.

– Interface is compatible with the ARM External Bus Interface (EBI).

6.5 Multi-Port Memory Controller (MPMC)

The multi-port memory controller supports the interface to different memory types, for

example:

• SDRAM

• Low-power SDRAM

• Static memory interface

This module has the following features:

• Dynamic memory interface support including SDRAM, JEDEC low-power SDRAM.

• Address line supporting up to 128 MB of dynamic memory.

• The MPMC has two AHB interfaces:

a. an interface for accessing external memory.

b. a separate control interface to program the MPMC. This enables the MPMC

registers to be situated in memory with other system peripheral registers.

• Low transaction latency.

• Read and write buffers to reduce latency and to improve performance, particularly for

un-cached processors.

• Static memory features include:

– asynchronous page mode read

– programmable wait states

– bus turnaround delay

– output enable and write enable delays

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